View 24LCS21-13_8466689.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 1995-2012 microchip technology inc. ds21127g-page 1 24lcs21 features: ? completely implements ddc1 ? /ddc2 ? interface for monitor identification ? hardware write-protect pin ? single supply with operation down to 2.5v ? low-power cmos technology: - 1 ma active current, typical -10 ? a standby current, typical at 5.5v ? 2-wire serial interface bus, i 2 c ? compatible (scl) ? self-timed write cycle (including auto-erase) ? page-write buffer for up to 8 bytes ? 100 khz (2.5v) and 400 khz (5v) compatibility (scl) ? 1,000,000 erase/write cycles ensured ? data retention > 200 years ? 8-pin pdip and soic package ? available for extended temperature ranges: description: the microchip technology inc. 24lcs21 is a 128 x 8-bit dual-mode electrically erasable prom. this device is designed for use in applications requiring storage and serial transmission of configuration and control informa- tion. two modes of operation have been implemented: transmit-only mode and bidirectional mode. upon power-up, the device will be in the transmit-only mode, sending a serial bit stream of the entire memory array contents, clocked by the v clk pin. a valid high-to-low transition on the scl pin will cause the device to enter the bidirectional mode, with byte selectable read/write capability of the memory array in standard i 2 c protocol. the 24lcs21 also enables the user to write-protect the entire memory contents using its write-protect pin. the 24lcs21 is available in a standard 8-pin pdip and soic package in both commercial and industrial temperature ranges. package types block diagram - commercial (c): 0c to +70c - industrial (i) -40c to +85c 24lcs21 soic 1 2 3 4 8 7 6 5 v cc v clk scl sda nc nc wp v ss 24lcs21 pdip 1 2 3 4 8 7 6 5 v cc v clk scl sda nc nc wp v ss i/o control logic eeprom array page latches hv generator sense amp r/w control memory control logic xdec ydec v cc v ss sda scl v clk wp 1k 2.5v dual mode i 2 c ? serial eeprom not recommended for new designs ? please use 24lcs21a.
24lcs21 ds21127g-page 2 ? 1995-2012 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................7.0v all inputs and outputs w.r.t. v ss ........................................................................................................ -0.6v to v cc + 1.0v storage temperature ............................................................................................................ ...................-65 ? c to +150 ? c ambient temperature with power applied ......................................................................................... .......-40 ? c to +125 ? c soldering temperature of leads (10 seconds) .................................................................................... ...................+300 ? c esd protection on all pins ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????????????? ?????????????????????????? 4 kv table 1-1: dc characteristics ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics v cc = +2.5v to 5.5v commercial (c): t a = 0 ? c to +70 ? c industrial (i): t a = - 40 ? c to +85 ? c parameter symbol min max units conditions scl and sda pins: high-level input voltage low-level input voltage v ih v il 0.7 v cc 0.3 v cc v v input levels on v clk pin: high-level input voltage low-level input voltage v ih v il 2.0 0.8 0.2 v cc v v v cc ? 2.7v (note 1) v cc < 2.7v (note 1) hysteresis of schmitt trigger inputs v hys .05 v cc ?v (note 1) low-level output voltage v ol 1 0.4 v i ol = 3 ma, v cc = 2.5v (note 1) low-level output voltage v ol 2 0.6 v i ol = 6 ma, v cc = 2.5v input leakage current i li -10 10 ? av in = 0.1v to v cc output leakage current i lo -10 10 ? av out = 0.1v to v cc pin capacitance (all inputs/outputs) c int 10 pf v cc = 5.0v (note 1) , t a = 25 ? c, f clk = 1 mhz operating current i cc write i cc read ? ? 3 1 ma ma v cc = 5.5v, scl = 400 khz standby current i ccs ?30 100 ? a ? a v cc = 3.0v, sda = scl = v cc v cc = 5.5v, sda = scl = v cc v clk = v ss note 1: this parameter is periodically sampled and not 100% tested.
? 1995-2012 microchip technology inc. ds21127g-page 3 24lcs21 table 1-2: ac characteristics parameter symbol v cc = 2.5-5.5v v cc = 4.5-5.5v units remarks min max min max clock frequency f clk 01000400khz clock high time t high 4000 ? 600 ? ns clock low time t low 4700 ? 1300 ? ns sda and scl rise time t r ? 1000 ? 300 ns (note 1) sda and scl fall time t f ? 300 ? 300 ns (note 1) start condition hold time t hd : sta 4000 ? 600 ? ns after this period the first clock pulse is generated start condition setup time t su : sta 4700 ? 600 ? ns only relevant for repeated start condition data input hold time t hd : dat 0?0?ns (note 2) data input setup time t su : dat 250 ? 100 ? ns stop condition setup time t su : sto 4000 ? 600 ? ns output valid from clock t aa ? 3500 ? 900 ns (note 2) bus free time t buf 4700 ? 1300 ? ns time the bus must be free before a new transmission can start output fall time from v ih minimum to v il maximum t of ? 250 20 + 0.1 c b 250 ns (note 1) , c b ?? 100 pf input filter spike suppression (sda and scl pins) t sp ?100? 50ns (note 3) write cycle time t wr ? 10 ? 10 ms byte or page mode transmit-only mode parameters output valid from v clk t vaa ? 2000 ? 1000 ns v clk high time t vhigh 4000 ? 600 ? ns v clk low time t vlow 4700 ? 1300 ? ns v clk setup time t vhst 0?0?ns v clk hold time t spvl 4000 ? 600 ? ns mode transition time t vhz ? 500 ? 500 ns transmit-only power-up time t vpu 0?0?ns input filter spike suppression (v clk pin) t spv ? 100 ? 100 ns endurance ? 1m ? 1m ? cycles 25c, v cc = 5.0v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to schmitt trigger inputs which provide noise and spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance ? model which can be obtained from microchip?s web site at www.microchip.com.
24lcs21 ds21127g-page 4 ? 1995-2012 microchip technology inc. 2.0 functional description the 24lcs21 operates in two modes, the transmit- only mode and the bidirectional mode. there is a separate two-wire protocol to support each mode, each having a separate clock input but sharing a common data line (sda). the device enters the transmit-only mode upon power-up. in this mode, the device transmits data bits on the sda pin in response to a clock signal on the v clk pin. the device will remain in this mode until a valid high-to-low transition is placed on the scl input. when a valid transition on scl is recognized, the device will switch into the bidirectional mode. the only way to switch the device back to the transmit-only mode is to remove power from the device. 2.1 transmit-only mode the device will power-up in the transmit-only mode at address 00h. this mode supports a unidirectional two- wire protocol for continuous transmission of the contents of the memory array. this device requires that it be initialized prior to valid data being sent in the transmit-only mode (see initialization procedure, below). in this mode, data is transmitted on the sda pin in 8-bit bytes, with each byte followed by a ninth, null bit (figure 2-1). the clock source for the transmit-only mode is provided on the v clk pin, and a data bit is out- put on the rising edge on this pin. the eight bits in each byte are transmitted most significant bit first. each byte within the memory array will be output in sequence. when the last byte in the memory array is transmitted, the internal address pointers will wrap around to the first memory location (00h) and continue. the bidirectional mode clock (scl) pin must be held high for the device to remain in the transmit-only mode. 2.2 initialization procedure after v cc has stabilized, the device will be in the trans- mit-only mode. nine clock cycles on the v clk pin must be given to the device for it to perform internal synchro- nization. during this period, the sda pin will be in a high-impedance state. on the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit in address 00h. (figure 2-2). figure 2-1: transmit-only mode figure 2-2: device initialization scl sda v clk t vaa t vaa bit 1 (lsb) null bit bit 1 (msb) bit 7 t vlow t vhigh t vaa t vaa bit 8 bit 7 high-impedance for 9 clock cycles t vpu 12 891011 scl sda v clk v cc
? 1995-2012 microchip technology inc. ds21127g-page 5 24lcs21 3.0 bidirectional mode the 24lcs21 can be switched into the bidirectional mode (figure 3-1) by applying a valid high-to-low transition on the bidirectional mode clock (scl). when the device has been switched into the bidirectional mode, the v clk input is disregarded, with the exception that a logic high level is required to enable write capa- bility. this mode supports a two-wire bidirectional data transmission protocol (i 2 c ? ). in this protocol, a device that sends data on the bus is defined to be the transmit- ter and a device that receives data from the bus is defined to be the receiver. the bus must be controlled by a master device that generates the bidirectional mode clock (scl), controls access to the bus and gen- erates the start and stop conditions, while the 24lcs21 acts as the slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. in this mode, the 24lcs21 only responds to commands for device ? 1010 000x ?. 3.1 bidirectional mode bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 3-2). 3.1.1 bus not busy (a) both data and clock lines remain high. 3.1.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.1.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. figure 3-1: mode transition figure 3-2: data transfer sequence on the serial bus scl sda v clk bidirectional mode t vhz transmit-only mode (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition scl sda
24lcs21 ds21127g-page 6 ? 1995-2012 microchip technology inc. 3.1.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. when an overwrite does occur, it will replace data in a first-in first-out (fifo) fashion. 3.1.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figure 3-3: bus timing start/stop figure 3-4: bus timing data note: once switched into bidirectional mode, the 24lcs21 will remain in that mode until power goes away. removing power is the only way to reset the 24lcs21 into the transmit-only mode. note: the 24lcs21 does not generate any acknowledge bits if an internal programming cycle is in progress. t su : sta t hd : sta v hys t su : sto start stop scl sda scl sda in sda out t su : sta t sp t aa t f t low t high t hd : sta t hd : dat t su : dat t su : sto t buf t aa t r
? 1995-2012 microchip technology inc. ds21127g-page 7 24lcs21 3.1.6 slave address after generating a start condition, the bus master transmits the slave address consisting of a 7-bit device code ? 1010000 ? for the 24lcs21. the eighth bit of the slave address determines whether the master device wants to read or write to the 24lcs21 (figure 3-5). the 24lcs21 monitors the bus for its corresponding slave address continuously. it generates an acknowledge bit if the slave address was true and it is not in a programming mode. figure 3-5: control byte allocation operation slave address r/w read 1010000 1 write 1010000 0 slave address 101000 0 r/ w a start read/write
24lcs21 ds21127g-page 8 ? 1995-2012 microchip technology inc. 4.0 write operation 4.1 byte write following the start signal from the master, the slave address (4 bits), three zero bits ( 000 ) and the r/w bit, which is a logic low, are placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24lcs21. after receiving another acknowledge signal from the 24lcs21, the master device will transmit the data word to be written into the addressed memory location. the 24lcs21 acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time the 24lcs21 will not generate acknowledge signals (figure 4-1). it is required that v clk be held at a logic high level during command and data transfer in order to program the device. this applies to both byte write and page write operation. note, however, that the v clk is ignored during the self-timed program operation. changing v clk from high-to-low during the self-timed program operation will not halt programming of the device. figure 4-1: byte write figure 4-2: vclk write enable timing bus activity sda line bus activity control byte word address data s t o p s t a r t a c k s p a c k a c k v clk activity t spvl t su : sto t hd : sta t vhst v clk sda in scl
? 1995-2012 microchip technology inc. ds21127g-page 9 24lcs21 4.2 page write the write control byte, word address and the first data byte are transmitted to the 24lcs21 in the same way as in a byte write. but instead of generating a stop condition, the master transmits up to eight data bytes to the 24lcs21, which are temporarily stored in the on- chip page buffer and will be written into the memory after the master has transmitted a stop condition. after the receipt of each word, the three lower order address pointer bits are internally incremented by one. the higher order five bits of the word address remains constant. if the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an internal write cycle will begin (figure 5-2). it is required that v clk be held at a logic high level during command and data transfer in order to program the device. this applies to both byte write and page write operation. note, however, that the v clk is ignored during the self-timed program operation. changing v clk from high-to-low during the self-timed program operation will not halt programming of the device. note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size ? 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
24lcs21 ds21127g-page 10 ? 1995-2012 microchip technology inc. 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 5-1 for the flow diagram. figure 5-1: acknowledge polling flow figure 5-2: page write did device acknowledge (ack = 0 )? send write command send stop condition to initiate write cycle send start send control byte with r/ w = 0 next operation no yes bus master sda line bus control byte word address s t o p s t a r t a c k a c k a c k activity activity a c k a c k data n + 1 data n + 7 data (n) p s v clk
? 1995-2012 microchip technology inc. ds21127g-page 11 24lcs21 6.0 write protection when using the 24lcs21 in the bidirectional mode, the v clk pin operates as the write-protect control pin. set- ting v clk high allows normal write operations, while setting v clk low prevents writing to any location in the array. connecting the v clk pin to v ss would allow the 24lcs21 to operate as a serial rom, although this configuration would prevent using the device in the transmit-only mode. additionally, pin 3 performs a flexible write-protect function. the 24lcs21 contains a write protection control fuse whose factory default state is cleared. writing any data to address 7fh (normally the checksum in ddc applications) sets the fuse which enables the wp pin. until this fuse is set, the 24lcs21 is always write enabled (if v clk = 1 ). after the fuse is set, the write capability of the 24lcs21 is determined by wp (figure 6-1). table 6-1: write-protect truth table 7.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read and sequential read. 7.1 current address read the 24lcs21 contains an address counter that maintains the address of the last word accessed, internally incremented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to one, the 24lcs21 issues an acknowledge and transmits the eight-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24lcs21 discontinues transmission (figure 7-1). figure 7-1: current address read 7.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24lcs21 as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. the 24lcs21 will then issue an acknowledge and transmits the eight-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24lcs21 discontinues transmission (figure 7-2). v clk wp add. 7fh written mode 0xx read-only 1x no r/w 11 /open yes r/w 10 yes read-only control a c k s s t a r t s t o p p byte data n bus activity sda line bus activity a c k n o master 101 0000 1
24lcs21 ds21127g-page 12 ? 1995-2012 microchip technology inc. figure 7-2: random read 7.3 sequential read sequential reads are initiated in the same way as a random read except that after the 24lcs21 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24lcs21 to transmit the next sequentially addressed 8-bit word (figure 8-1). to provide sequential reads, the 24lcs21 contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 7.4 noise protection the 24lcs21 employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5 volts at nominal conditions. the sda, scl and v clk inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. bus activity master sda line bus activity control byte word address data n a c k s t a r t n o s t a r control byte a c k a c k a c k ss t p s t o p 10100000 0 0 0 0 01 1 1
? 1995-2012 microchip technology inc. ds21127g-page 13 24lcs21 8.0 pin descriptions table 8-1: pin function table 8.1 sda this pin is used to transfer addresses and data into and out of the device, when the device is in the bidirectional mode. in the transmit-only mode, which only allows data to be read from the device, data is also transferred on the sda pin. this pin is an open drain terminal, therefore the sda bus requires a pull-up resistor to v cc (typical 10 k ? for 100 khz, 2 k ? for 400 khz). for normal data transfer in the bidirectional mode, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 8.2 scl this pin is the clock input for the bidirectional mode, and is used to synchronize data transfer to and from the device. it is also used as the signaling input to switch the device from the transmit-only mode to the bidirectional mode. it must remain high for the chip to continue operation in the transmit-only mode. 8.3 vclk this pin is the clock input for the transmit-only mode (ddc1). in the transmit-only mode, each bit is clocked out on the rising edge of this signal. in the bidirectional mode, a high logic level is required on this pin to enable write capability. 8.4 w p this pin is used for flexible write protection of the 24lcs21. when the last memory location (7fh) is written with any data, this pin is enabled and determines the write capability of the 24lcs21 (figure 6-1). figure 8-1: sequential read name function wp write-protect (active low) v ss ground sda serial address/data i/o scl serial clock (bidirectional mode) v clk serial clock (transmit-only mode) v cc +2.5v to 5.5v power supply nc no connection a c k p bus activity master sda line bus activity control byte data n data n+1 data n+2 data n+x a c k a c k a c k n o a c k s t o p
24lcs21 ds21127g-page 14 ? 1995-2012 microchip technology inc. 9.0 packaging information 9.1 package marking information xxxxxnnn 8-lead pdip xxxxxxxx yyww 017 example 24lcs21 0410 8-lead soic (.150?) xxxxxxxx xxxxyyww nnn example 24lcs21 /sn0410 017 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
? 1995-2012 microchip technology inc. ds21127g-page 15 24lcs21 8-lead plastic dual in-line (p) ? 300 mil body (pdip) b1 b a1 a l a2 p ? e eb ? c e1 n d 1 2 units inches * millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top ? 5 10 15 5 10 15 mold draft angle bottom ? 5 10 15 5 10 15 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: ms-001 drawing no. c04-018 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
24lcs21 ds21127g-page 16 ? 1995-2012 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil body (soic) foot angle ? 048048 15 12 0 15 12 0 ? mold draft angle bottom 15 12 0 15 12 0 ? mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches * units 2 1 d n p b e e1 h l ? c 45 ? ? a2 ? a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1995-2012 microchip technology inc. ds21127g-page 17 24lcs21 appendix a: revision history revision e added note to page 1 header (not recommended for new designs). added section 9.0: package marking information. added on-line support page. updated document format. revision f revised section 8.4 revision g added a note to each package outline drawing.
24lcs21 ds21127g-page 18 ? 1995-2012 microchip technology inc. notes:
? 1995-2012 microchip technology inc. ds21127g-page 19 24lcs21 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
24lcs21 ds21127g-page 20 ? 1995-2012 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21127g 24lcs21 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 1995-2012 microchip technology inc. ds21127g-page 21 24lcs21 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support part no. x /xx xxx pattern package temperature range device device: 24lcs21: dual mode i 2 c serial eeprom 24lcs21t: dual mode i 2 c serial eeprom (tape and reel) temperature range: blank = 0 ? c to +70 ? c i= -40 ? c to +85 ? c package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead . data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
24lcs21 ds21127g-page 22 ? 1995-2012 microchip technology inc. notes:
? 1995-2012 microchip technology inc. ds21127g-page 23 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 1995-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620767313 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
ds21127g-page 24 ? 1995-2012 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - osaka tel: 81-66-152-7160 fax: 81-66-152-9310 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 10/26/12

▲Up To Search▲

Price & Availability of 24LCS21-13

	To Download 24LCS21-13 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .